1. Field of the Invention
Embodiments of the invention relate generally to surface treatments, such as those adapted for use in the polishing of a material surface useful in the fabrication of semiconductor devices.
2. Description of Related Art
Silicon carbide (SiC) is used extensively as a semiconductor material for many applications. Semiconductor devices formed on a SiC substrate have the ability to operate at higher voltages and temperatures than conventional devices formed on a silicon (Si) substrate. Indeed, for many high frequency, high temperature, high voltage, and/or hostile radiation environment applications, SiC is rapidly becoming the semiconductor material of choice.
SiC may be grown in many different polytypes, but 6H and 4H polytypes are widely used in industry. The “H” in these polytype designations refers to a hexagonal crystal structure, and the “4” or “6” denotes the number of steps before replication of the structure. Polytypes may be oriented “on” or “off” a primary crystal axis.
Regardless of polytype, SiC may be doped with elements that increase or decrease its resistivity. When SiC resistivity reaches levels greater than about 105 ohm-cm, it is considered semi-insulating. However, one current industry trend seeks to produce intrinsically pure semi-insulating SiC material which is not doped. The most common commercially available wafer types are 4H— and 6H—SiC, both conductive and semi-insulating, as well as on axis and up to 8° off axis. Wafers formed from SiC are used as substrates supporting the fabrication of semiconductor devices.
The performance qualities exhibited by semiconductor devices formed on a SiC substrate are greatly influenced by the structural integrity and smoothness of epitaxial films grown on the substrate. A smooth, defect-free surface is crucial to the epitaxial growth of high-quality thin films. Numerous studies of epitaxially grown thin films on 4H— and 6H—SiC substrate have shown that fabrication process induced defects in the substrate surface, such as scratches and/or subsurface damage introduced during lapping and polishing processes, are primary contributors to unwanted polytype inclusions in the subsequently grown epitaxial films.
Unfortunately, the material properties of SiC that provide its desirable characteristics also present difficult challenges to putative surface treatment techniques. For example, SiC is extremely hard, possessing a Mohs hardness of nine plus (9+). It is very chemically stable, and generally unaffected by exposure to acid or alkali at temperatures less than about 300° C.
Conventional surface treatments applied to SiC may be generally categorized as mechanical polishing, chemical-mechanical polishing (CMP), and etching. Mechanical polishing techniques are characterized by the use of very hard abrasives, such as diamond grit, applied to the surface of a SiC wafer. While mechanical polishing effectively removes surface material, it often results in a rough and/or damaged wafer surface. Conventional etching techniques applied to SiC wafers are performed at high temperature, and while potentially useful in the localized planarization of the wafer surface are ill-suited to global planarization objectives.
As a result of the deficiencies noted in mechanical polishing and etching techniques, significant research has been directed to improving CMP techniques. CMP techniques generally combine mechanical polishing with chemical etching to provide a wafer surface having decreased overall roughness and less damage to subsurface layers. In a recent technical paper, one conventional CMP method was proposed wherein a concentrated colloidal silica slurry having high pH (e.g., a pH higher than 10) was applied at elevated temperatures (e.g., 55° C.) to the Si-terminated surface of a SiC wafer. See, I. Electrochem. Soc. Vol. 144, No. 6, June 1997, the subject matter of which is hereby incorporated by reference. Similarly, in patent document WO 2005/099388 A2, the subject matter of which is hereby incorporated by reference, another conventional CMP method was proposed wherein a high pH (e.g., 8 to 14) solution containing colloidal silica or alumina was used to polish an SI wafer.
Due to the hardness of SiC, multiple surface treatments or surface treatment cycles are often applied before an acceptable surface is obtained. Mechanical polishing using diamond grit remains the industry standard, at least in the early stages (or cycles) of SiC surface treatment. Typical practice involves the slicing of SiC wafers from a crystalline boule using a wire saw having a fixed diamond abrasive or a wire carrying a mixture of diamond and boron carbide grits in a slurry solution. To remove the wafer surface damage resulting from the cutting process, SiC wafers are fixed to a platen and then lapped and polished with a succession of smaller size diamond grits on a conventional polishing machine. This is typically a 4-step process beginning with a 3-micron diamond grit, moving to a 1-micron diamond grit, and then to a 0.25-micron diamond grit. The final polishing step is often a conventional CMP process using colloidal silica.
However, as will be seen in some additional detail by way of comparison to embodiments of the invention, conventional surface treatment techniques simply do not work well—particularly when applied to wide-bandgap material such as SiC. Among other deficiencies apparent in conventional surface treatment techniques, selective etching of scratches and other surface defects may actually increase the overall roughness of a wafer surface. That is, conventional surface treatment techniques often remove equal amounts of material from the working wafer surface and scratches and other defects present in the working surface. Thus, scratches and surface defects are merely propagated down into the wafer surface by the conventional surface treatments. Worse still, some conventional surface treatments selectively etch the scratches and surface defects to a greater degree than the working wafer surface, thereby deepening and/or expanding the scratch or defect.
A non-selective—relative to scratches and other surface defects formed in a wafer surface—surface treatment process is needed. At a minimum, the non-selective process should work on all major polytypes of SiC, including at least 6H and 4H polytypes, whether the SiC wafer is formed off-axis and on-axis, and whether the SiC wafer is conductive or semi-insulating in nature.